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rev. f - 15 february, 2001 1 t89c51rd2 0 to 40mhz flash programmable 8-bit microcontroller 1. description atmel wireless and microcontrollers t89c51rd2 is high performance cmos flash version of the 80c51 cmos single chip 8-bit microcontroller. it contains a 64 kbytes flash memory block for program and for data. the 64 kbytes flash memory can be programmed either in parallel mode or in serial mode with the isp capability or with software. the programming voltage is internally generated from the standard v cc pin. the t89c51rd2 retains all features of the atmel wireless and microcontrollers 80c52 with 256 bytes of internal ram, a 7-source 4-level interrupt controller and three timer/counters. in addition, the t89c51rd2 has a programmable counter array, an xram of 1024 bytes, an eeprom of 2048 bytes, a hardware watchdog timer, a more versatile serial channel that facilitates multiprocessor communication (euart) and a speed improvement mechanism (x2 mode). pinout is either the standard 40/ 44 pins of the c52 or an extended version with 6 ports in a 64/68 pins package. the fully static design of the t89c51rd2 allows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the t89c51rd2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the peripherals and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. the added features of the t89c51rd2 makes it more powerful for applications that need pulse width modulation, high speed i/o and counting capabilities such as alarms, motor control, corded phones, smart card readers. 2. features 80c52 compatible 8051 pin and instruction compatible four 8-bit i/o ports (or 6 in 64/68 pins packages) three 16-bit timer/counters 256 bytes scratch pad ram 7 interrupt sources with 4 priority levels isp (in system programming) using standard v cc power supply. boot flash contains low level flash programming routines and a default serial loader high-speed architecture 40 mhz in standard mode 20 mhz in x2 mode (6 clocks/machine cycle) 64k bytes on-chip flash program / data memory byte and page (128 bytes) erase and write 10k write cycles on-chip 1024 bytes expanded ram (xram) software selectable size (0, 256, 512, 768, 1024 bytes) 768 bytes selected at reset for t87c51rd2 compatibility dual data pointer variable length movx for slow ram/peripherals improved x2 mode with independant selection for cpu and each peripheral 2 k bytes eeprom block for data storage 100k write cycle programmable counter array with: high speed output, compare / capture, pulse width modulator, watchdog timer capabilities asynchronous port reset full duplex enhanced uart low emi (inhibit ale) hardware watchdog timer (one-time enabled with reset-out) power control modes: idle mode. power-down mode.
2 rev. f - 15 february, 2001 t89c51rd2 power supply: - m version: commercial and industrial 4.5v to 5.5v : 40mhz x1 mode, 20mhz x2 mode 3v to 5.5v : 33mhz x1 mode, 16 mhz x2 mode - l version: commercial and industrial 2.7v to 3.6v : 25mhz x1 mode, 12mhz x2 mode temperature ranges: commercial (0 to +70 c) and industrial (-40 to +85 c). packages: pdil40, plcc44, vqfp44, plcc68, vqfp64 table 1. memory size 3. block diagram pdil40 plcc44 vqfp44 1.4 flash (bytes) eeprom (bytes) xram (bytes) total ram (bytes) i/o t89c51rd2 64k 2k 1024 1280 32 plcc68 vqfp64 1.4 flash (bytes) eeprom (bytes) xram (bytes) total ram (bytes) i/o t89c51rd2 64k 2k 1024 1280 48 timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea psen ale/ xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 (3) (3) c51 core (3) (3) (3) (3) port 0 p0 port 1 port 2 port 3 parallel i/o ports & ext. bus p1 p2 p3 xram 1kx8 ib-bus pca reset prog watch dog pca eci vss v cc (3) (3) (1) (1): alternate function of port 1 (3): alternate function of port 3 (1) timer2 t2ex t2 (1) (1) port 5 port 4 p5 p4 (2): only available on high pin count packages (2) (2) flash 64kx8 eeprom 2kx8
rev. f - 15 february, 2001 3 t89c51rd2 4. sfr mapping the special function registers (sfrs) of the t89c51rd2 fall into the following categories: c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 i/o port registers: p0, p1, p2, p3, p4, p5 timer registers: t2con, t2mod, tcon, th0, th1, th2, tmod, tl0, tl1, tl2, rcap2l, rcap2h serial i/o port registers: saddr, saden, sbuf, scon power and clock control registers: pcon hardware watchdog timer register: wdtrst, wdtprg interrupt system registers: ie, ip, iph flash and eeprom registers: fcon, eecon, eetim others: auxr, auxr1, ckcon table below shows all sfrs with their address and their reset value. bit address- able non bit addressable 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h xxxx xxxx ccap1h xxxx xxxx ccapl2h xxxx xxxx ccapl3h xxxx xxxx ccapl4h xxxx xxxx ffh f0h b 0000 0000 f7h e8h p5 1111 1111 cl 0000 0000 ccap0l xxxx xxxx ccap1l xxxx xxxx ccapl2l xxxx xxxx ccapl3l xxxx xxxx ccapl4l xxxx xxxx efh e0h acc 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 fcon xxxx 0000 eecon xxxx xx00 eetim 0000 0000 d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h p4 1111 1111 p5 1111 1111 c7h b8h ip x000 000 saden 0000 0000 bfh b0h p3 1111 1111 iph x000 0000 b7h a8h ie 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx 00x0 wdtrst xxxx xxxx wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf xxxx xxxx 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr xx0x 1000 ckcon x000 0000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f
4 rev. f - 15 february, 2001 t89c51rd2 reserved
rev. f - 15 february, 2001 5 t89c51rd2 5. pin configuration p1.7cex4 p1.4/cex1 rst p3.0/rxd p3.1/txd p1.3cex0 1 p1.5/cex2 p1.6/cex3 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/ad8 p2.1/ad9 p2.2/ad10 p2.3/ad11 p2.4/ad12 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea p2.7/ad15 p2.5/ad13 p2.6/ad14 p1.0/t2 p1.2/eci p1.1/t2ex vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 pdil 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 18 19 23 22 21 20 26 25 24 27 28 5 4 3 2 1 6 44 43 42 41 40 p1.4/cex1 p1.0/t2 p1.1/t2ex p1.3/cex0 p1.2/eci vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea nic* p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 43 42 41 40 39 44 38 37 36 35 34 p1.4/cex1 p1.0/t2 p1.1/t2ex p1.3/cex0 p1.2/eci vss1/nic* vcc p0.0/ad0 p0.2/ad2 p0.3/ad3 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale/prog psen ea nic* p2.7/a15 p2.5/a13 p2.6/a14 p1.5/cex2 p1.6/cex3 p1.7/cex4 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5/cex2 p1.6/cex3 p1.7/cex4 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 nic* nic* *nic: no internal connection 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 plcc 12 13 17 16 15 14 20 19 18 21 22 33 32 31 30 29 28 27 26 25 24 23 vqfp44 1.4 1 2 3 4 5 6 7 8 9 10 11
6 rev. f - 15 february, 2001 t89c51rd2 12 10 15 14 13 11 16 17 18 19 20 21 22 23 24 25 26 p5.5 p0.3/ad3 p0.2/ad2 p5.6 p0.1/ad1 p0.0/ad0 p5.7 vcc vss1 p1.0/t2 p4.0 p1.1/t2ex p1.2/eci p1.3/cex0 p4.1 p1.4/cex1 p4.2 2 3 5 6 7 4 1 686766656463 60 59 58 57 56 55 36 37 38 39 40 41 29 30 31 32 33 34 35 27 28 42 43 48 49 50 51 52 53 54 psen p5.3 p0.5/ad5 p0.6/ad6 nic p0.7/ad7 ea nic ale/pro g nic p2.7/a15 p2.6/a14 p5.2 p0.4/ad4 p5.4 p5.1 p2.5/a13 nic p1.7/cex4 rst nic nic nic p3.0/rxd nic nic nic p3.1/txd p3.3/int1 p5.0 p2.4/a12 p2.3/a11 p4.7 p2.2/a10 p2.1/a9 p2.0/a8 vss p4.6 p4.5 xtal1 xtal2 nic plcc 68 8 9 62 61 p1.5/cex2 p1.6/cex3 p3.4/t0 p3.5/t1 44 45 46 47 p4.4 p3.6/wr p4.3 p3.7/rd p3.2/int0 psen p5.4 p5.3 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea nic ale/prog p2.7/a15 p2.6/a14 p5.2 p5.1 p2.5/a13 p5.0 p0.4/ad4 58 50 51 52 53 54 55 56 57 59 60 61 62 63 64 49 vss p2.3/a11 p4.7 p2.2/a10 p2.1/a9 p2.0/a8 p4.6 p4.5 nic xtal1 xtal2 p3.7/rd p4.4 p4.3 p2.4/a12 p3.6/wr 42 34 35 36 37 38 39 40 41 43 44 45 46 47 48 33 p1.0/t2 p0.3/ad3 p0.2/ad2 p5.6 p0.1/ad1 p0.0/ad0 p5.7 vcc vss1 p4.0 p1.1/t2ex p1.2/ec1 p1.3/cex0 p4.1 p1.4/cex1 p5.5 7 15 14 13 12 11 10 9 8 6 5 4 3 2 1 16 nic p3.4/t0 p3.2/int0 p3.1/txd nic nic p3.0/rxd nic nic rst p1.7/cex4 p1.6/cex3 p1.5/cex2 p4.2 p3.5/t1 26 18 19 20 21 22 23 24 25 27 28 29 30 31 32 17 vqfp64 1.4 p3.3/int1 nic: no internalconnection
rev. f - 15 february, 2001 7 t89c51rd2 mnemonic pin number type name and function dil lcc vqfp 1.4 v ss 20 22 16 i ground: 0v reference vss1 1 39 i optional ground: contact the sales office for ground connection. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle and power- down operation p0.0-p0.7 39-32 43-36 37-30 i/o port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. port 0 must be polarized to v cc or v ss in order to prevent any parasitic current consumption. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. port 0 also inputs the code bytes during eprom programming. external pull-ups are required during program verification during which p0 outputs the code bytes. p1.0-p1.7 1-8 2-9 40-44 1-3 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. port 1 also receives the low-order address byte during memory programming and verification. alternate functions for tsc8x54/58 port 1 include: 1 2 40 i/o t2 (p1.0): timer/counter 2 external count input/clockout 2 3 41 i t2ex (p1.1): timer/counter 2 reload/capture/direction control 3 4 42 i eci (p1.2): external clock for the pca 4 5 43 i/o cex0 (p1.3): capture/compare external i/o for pca module 0 5 6 44 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 6 7 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 7 8 2 i/o cex3 (p1.6): capture/compare external i/o for pca module 3 8 9 3 i/o cex4 (p1.7): capture/compare external i/o for pca module 4 p2.0-p2.7 21-28 24-31 18-25 i/o port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr).in this application, it uses strong internal pull-ups emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. some port 2 pins receive the high order address bits during eprom programming and verification: p2.0 to p2.5 for rb devices p2.0 to p2.6 for rc devices p2.0 to p2.7 for rd devices. p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 0 13 15 9 i int1 (p3.3): external interrupt 1 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe
8 rev. f - 15 february, 2001 t89c51rd2 mnemonic pin number type name and function dil lcc vqfp 1.4 17 19 13 o rd (p3.7): external data memory read strobe reset 9 10 4 i/o reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . this pin is an output when the hardware watchdog forces a system reset. ale/ prog 30 33 27 o (i) address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (1/3 in x2 mode) the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input ( prog) during flash programming. ale can be disabled by setting sfrs auxr.0 bit. with this bit set, ale will be inactive during internal fetches. psen 29 32 26 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea 31 35 29 i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to ffffh (rd). if security level 1 is programmed, ea will be internally latched on reset. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier
rev. f - 15 february, 2001 9 t89c51rd2 5.1. pin description for 64/68 pin packages port 4 and port 5 are 8-bit bidirectional i/o ports with internal pull-ups. pins that have 1 written to them are pulled high by the internal pull ups and can be used as inputs. as inputs, pins that are externally pulled low will source current because of the internal pull-ups. refer to the previous pin description for other pins. plcc68 square vqfp64 1.4 vss 51, 18 9/40 vcc 17 8 p0.0 15 6 p0.1 14 5 p0.2 12 3 p0.3 11 2 p0.4 9 64 p0.5 6 61 p0.6 5 60 p0.7 3 59 p1.0 19 10 p1.1 21 12 p1.2 22 13 p1.3 23 14 p1.4 25 16 p1.5 27 18 p1.6 28 19 p1.7 29 20 p2.0 54 43 p2.1 55 44 p2.2 56 45 p2.3 58 47 p2.4 59 48 p2.5 61 50 p2.6 64 53 p2.7 65 54 p3.0 34 25 p3.1 39 28 p3.2 40 29 p3.3 41 30 p3.4 42 31 p3.5 43 32 p3.6 45 34 p3.7 47 36 reset 30 21 ale/ prog 68 56 psen 67 55 ea 2 58 xtal1 49 38 xtal2 48 37 p4.0 20 11 p4.1 24 15 p4.2 26 17 p4.3 44 33 p4.4 46 35 p4.5 50 39 p4.6 53 42 p4.7 57 46 p5.0 60 49 p5.1 62 51 p5.2 63 52 p5.3 7 62 p5.4 8 63 p5.5 10 1 p5.6 13 4 p5.7 16 7
rev. f - 15 february, 2001 10 t89c51rd2 6. enhanced features in comparison to the original 80c52, the t89c51rd2 implements some new features, which are : the x2 option. the dual data pointer. the extended ram. the programmable counter array (pca). the watchdog. the 4 level interrupt priority system. the power-off flag. the once mode. the ale disabling. some enhanced features are also located in the uart and the timer 2. 6.1. x2 feature and clock generation the t89c51rd2 core needs only 6 clock periods per machine cycle. this feature called x2 provides the following advantages: divide frequency crystals by 2 (cheaper crystals) while keeping same cpu power. save power consumption while keeping same cpu power (oscillator power saving). save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. increase cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by software. 6.1.1. description the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 1. shows the clock generation block diagram. x2 bit is validated on xtal1 ? 2 rising edge to avoid glitches when switching from x2 to std mode. figure 2. shows the mode switching waveforms. figure 1. clock generation diagram xtal1 2 ckcon reg x2 state machine: 6 clock cycles. cpu control f osc f xtal 0 1 xtal1:2
11 rev. f - 15 february, 2001 t89c51rd2 figure 2. mode switching waveforms the x2 bit in the ckcon register (see table 2.) allows to switch from 12 clock periods per instruction to 6 clock periods and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode). the t0x2, t1x2, t2x2, six2, pcax2 and wdx2 bits in the ckcon register (see table 2.) allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). these bits are active only in x2 mode. more information about the x2 mode can be found in the application note anm072 "how to take advantage of the x2 features in ts80c51 microcontroller?" table 2. ckcon register ckcon - clock control register (8fh) 7 6 5 4 3 2 1 0 - wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7 - reserved 6 wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5 pcax2 programmable counter array clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4 six2 enhanced uart clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3 t2x2 timer2 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2 t1x2 timer1 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode
rev. f - 15 february, 2001 12 t89c51rd2 reset value = x000 0000b not bit addressable 1 t0x2 timer0 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 0 x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2" bits. bit number bit mnemonic description
rev. f - 15 february, 2001 13 t89c51rd2 6.2. dual data pointer register ddptr the additional data pointer can be used to speed up code execution and reduce code size. the dual dptr structure is a way by which the chip will specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 3.) that allows the program code to switch between them (refer to figure 3). figure 3. use of dual pointer table 3. auxr1: auxiliary register 1 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a source pointer and the other one as a "destination" pointer. assembly language auxr1 address 0a2h - - - - gf3 0 - dps reset value x x x x 0 0 x 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new feature. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. b. bit 2 stuck at 0; this allows to use inc auxr1 to toggle dps without changing gf3. dps data pointer selection. dps operating mode 0 dptr0 selected 1 dptr1 selected gf3 this bit is a general purpose user flag b . external data memory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1
14 rev. f - 15 february, 2001 t89c51rd2 ; block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. observe that without the last instruction (inc auxr1), the routine will exit with dps in the opposite state.
rev. f - 15 february, 2001 15 t89c51rd2 6.3. expanded ram (xram) the t89c51rd2 provide additional bytes of random access memory (ram) space for increased data parameter handling and high level language usage. t89c51rd2 devices have expanded ram in external data space; maximum size and location are described in table 4. the t89c51rd2 has internal data memory that is mapped into four separate segments. the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the expanded ram bytes are indirectly accessed by movx instructions, and with the extram bit cleared in the auxr register. (see ) the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfr. that means they have the same address, but are physically separate from sfr space. figure 4. internal and external data memory address when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h, # data ,accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0, # data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). table 4. description of expanded ram port xram size address start end t89c51rd2 1024 00h 3ffh xram upper 128 bytes internal ram lower 128 bytes internal ram special function register 80 80 00 ff or 3ff ff 00 ff external data memory 0000 0100 or 0400 ffff indirect accesses direct accesses direct or indirect accesses
16 rev. f - 15 february, 2001 t89c51rd2 the xram bytes can be accessed by indirect addressing, with extram bit cleared and movx instructions. this part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. the bits xrs0 and xrs1 are used to hide a part of the available xram as explained in table . this can be useful if external peripherals are mapped at addresses already used by the internal xram. with extram = 0, the xram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to xram will not affect ports p0, p2, p3.6 ( wr) and p3.7 ( rd) . for example, with extram = 0, movx @r0, # data where r0 contains 0a0h, accesses the xram at address 0a0h rather than external memory. an access to external data memory locations higher than the accessible size of the xram will be performed with the movx dptr instructions in the same way as in the standard 80c51, so with p0 and p2 as data/address busses, and p3.6 and p3.7 as write and read timing signals. accesses to xram above 0ffh can only be done thanks to the use of dptr. with extram = 1, movx @ri and movx @dptr will be similar to the standard 80c51. movx @ ri will provide an eight-bit address multiplexed with data on port0 and any output port pins can be used to output higher order address bits. this is to provide the external paging capability. movx @dptr will generate a sixteen-bit address. port2 outputs the high-order eight address bits (the contents of dph) while port0 multiplexes the low-order eight address bits (dpl) with data. movx @ ri and movx @dptr will generate either read or write signals on p3.6 ( wr) and p3.7 ( rd). the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the xram. the m0 bit allows to stretch the xram timings; if m0 is set, the read and write pulses are extended from 6 to 30 clock periods. this is useful to access external slow peripherals. auxiliary register auxr auxr address 08eh - - m0 - xrs1 xrs0 extram ao reset value x x 0 x 1 0 0 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ao disable/enable ale ao operating mode 0 ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used) 1 ale is active only during a movx or movc instruction extram internal/external ram (00h-ffh) access using movx @ ri/ @ dptr extram operating mode 0 internal xram access using movx @ ri/ @ dptr 1 external data memory access xrs0 xrs1 xram size: accessible size of the xram xrs1:0 xram size 00 256 bytes 01 512 bytes 10 768 bytes (default) 11 1024 bytes m0 stretch movx control: the rd/ and the wr/ pulse length is increased according to the value of m0 m0 pulse length in clock period 0 6 1 30
rev. f - 15 february, 2001 17 t89c51rd2 6.4. timer 2 the timer 2 in the t89c51rd2 is compatible with the timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2, connected in cascade. it is controlled by t2con register (see table 5) and t2mod register (see table 6). timer 2 operation is similar to timer 0 and timer 1. c/ t2 selects f osc /12 (timer operation) or external pin t2 (counter operation) as the timer clock input. setting tr2 allows tl2 to be incremented by the selected input. timer 2 has 3 operating modes: capture, autoreload and baud rate generator. these modes are selected by the combination of rclk, tclk and cp/ rl2 (t2con), as described in the atmel wireless and micrcontrollers 8-bit microcontroller hardware description. refer to the atmel wireless and micrcontrollers 8-bit microcontroller hardware description for the description of capture and baud rate generator modes. in t89c51rd2 timer 2 includes the following enhancements: auto-reload mode with up or down counter programmable clock-output 6.4.1. auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. if dcen bit in t2mod is cleared, timer 2 behaves as in 80c52 (refer to the atmel wireless and micrcontrollers 8-bit microcontroller hardware description). if dcen bit is set, timer 2 acts as an up/down timer/counter as shown in figure 5. in this mode the t2ex pin controls the direction of count. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. exf2 does not generate any interrupt. this bit can be used to provide 17-bit resolution.
18 rev. f - 15 february, 2001 t89c51rd2 figure 5. auto-reload mode up/down counter (dcen = 1) 6.4.2. programmable clock-output in the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (see figure 6) . the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the rcap2h and rcap2l registers : for a 16 mhz system clock, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: set t2oe bit in t2mod register. clear c/ t2 bit in t2con register. determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or a different one depending on the application. to start the timer, set tr2 run control bit in t2con register. (down counting reload value) c/ t2 tf2 tr2 t2 exf2 th2 (8-bit) tl2 (8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh (8-bit) toggle (up counting reload value) timer 2 interrupt xtal1 : 12 f osc f xtal 0 1 t2conreg t2conreg t2conreg t2conreg t2ex: if dcen=1, 1=up if dcen=1, 0=down if dcen = 0, up counting clock outfrequency C f osc 4 65536 rcap 2 h C rcap 2 l () -------------------------------------------------------------------------------------- =
rev. f - 15 february, 2001 19 t89c51rd2 it is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 6. clock-out mode c/ t2=0 :2 exf2 tr2 oveflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2 xtal1 t2con reg t2con reg t2con reg t2mod reg interrupt qd toggle exen2
20 rev. f - 15 february, 2001 t89c51rd2 table 5. t2con register t2con - timer 2 control register (c8h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7 tf2 timer 2 over?ow flag must be cleared by software. set by hardware on timer 2 over?ow, if rclk = 0 and tclk = 0. 6 exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. when set, causes the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. exf2 doesnt cause an interrupt in up/down counter mode (dcen = 1) 5 rclk receive clock bit clear to use timer 1 over?ow as receive clock for serial port in mode 1 or 3. set to use timer 2 over?ow as receive clock for serial port in mode 1 or 3. 4 tclk transmit clock bit clear to use timer 1 over?ow as transmit clock for serial port in mode 1 or 3. set to use timer 2 over?ow as transmit clock for serial port in mode 1 or 3. 3 exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2 tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1 c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin, falling edge trigger). must be 0 for clock out mode. 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 over?ow. clear to auto-reload on timer 2 over?ows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
rev. f - 15 february, 2001 21 t89c51rd2 table 6. t2mod register t2mod - timer 2 mode control register (c9h) reset value = xxxx xx00b not bit addressable 7 6 5 4 3 2 1 0 - - - - - - t2oe dcen bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - reserved the value read from this bit is indeterminate. do not set this bit. 2 - reserved the value read from this bit is indeterminate. do not set this bit. 1 t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter.
rev. f - 15 february, 2001 22 t89c51rd2 6.5. programmable counter array pca the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accuracy. the pca consists of a dedicated timer/ counter which serves as the time base for an array of five compare/ capture modules. its clock input can be programmed to count any one of the following signals: oscillator frequency ? 12 ( ? 6 in x2 mode) oscillator frequency ? 4( ? 2 in x2 mode) timer 0 overflow external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. module 4 can also be programmed as a watchdog timer (see section "pca watchdog timer", page 31). when the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. the pca timer is a common time base for all five modules (see figure 7). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 7) and can be programmed to run at: 1/12 the oscillator frequency. (or 1/6 in x2 mode) 1/4 the oscillator frequency. (or 1/2 in x2 mode) the timer 0 overflow the input on the eci pin (p1.2) pca component external i/o pin 16-bit counter p1.2 / eci 16-bit module 0 p1.3 / cex0 16-bit module 1 p1.4 / cex1 16-bit module 2 p1.5 / cex2 16-bit module 3 p1.6 / cex3 16-bit module 4 p1.7 / cex4
23 rev. f - 15 february, 2001 t89c51rd2 figure 7. pca timer/counter table 7. cmod: pca counter mode register the cmod sfr includes three additional bits associated with the pca (see figure 7 and table 7). the cidl bit which allows the pca to stop during idle mode. the wdte bit which enables or disables the watchdog function on module 4. cmod address 0d9h cidl wdte - - - cps1 cps0 ecf reset value 0 0 x x x 0 0 0 symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cid l = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input. b b. f osc = oscillator frequency 0 0 internal clock f osc /12 ( or f osc /6 in x2 mode). 0 1 internal clock f osc /4 ( or f osc /2 in x2 mode). 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f osc /8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ec f = 0 disables that function of cf. cidl cps1 cps0 ecf it ch cl 16 bit up/down counter to pca modules fosc /12 fosc / 4 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 over?ow
rev. f - 15 february, 2001 24 t89c51rd2 the ecf bit which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to table 8). bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. bit cf: the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. table 8. ccon: pca counter control register the watchdog timer function is implemented in module 4 (see figure 10). the pca interrupt system is shown in figure 8 ccon address 0d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 reset value 0 0 x 0 0 0 0 0 symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software.
25 rev. f - 15 february, 2001 t89c51rd2 figure 8. pca interrupt system pca modules: each one of the five compare/capture modules has six possible functions. it can perform: 16-bit capture, positive-edge triggered, 16-bit capture, negative-edge triggered, 16-bit capture, both positive and negative-edge triggered, 16-bit software timer, 16-bit high speed output, 8-bit pulse width modulator. in addition, module 4 can be used as a watchdog timer. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 9). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. table 10 shows the ccapmn settings for the various pca functions. . cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea
rev. f - 15 february, 2001 26 t89c51rd2 table 9. ccapmn: pca modules compare/capture control registers table 10. pca module modes (ccapmn registers) there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 11 & table 12) ccapmn address n=0-4 ccapm0=0dah ccapm1=0dbh ccapm2=0dch ccapm3=0ddh ccapm4=0deh - ecomn cappn capnn matn togn pwmm eccfn reset value x 0 0 0 0 0 0 0 symbol function - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. ecomn cappn capnn matn togn pwmm eccfn module function 0 0 0 0 0 0 0 no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x 1 1 0 0 0 x 16-bit capture by a transition on cexn 100100x 16-bit software timer / compare mode. 1 0 0 1 1 0 x 16-bit high speed output 1 0 0 0 0 1 0 8-bit pwm 1 0 0 1 x 0 x watchdog timer (module 4 only)
27 rev. f - 15 february, 2001 t89c51rd2 table 11. ccapnh: pca modules capture/compare registers high table 12. ccapnl: pca modules capture/compare registers low table 13. ch: pca counter high table 14. cl: pca counter low 6.5.1. pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (refer to figure 9). ccapnh address n=0-4 ccap0h=0fah ccap1h=0fbh ccap2h=0fch ccap3h=0fdh ccap4h=0feh 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 ccapnl address n=0-4 ccap0l=0eah ccap1l=0ebh ccap2l=0ech ccap3l=0edh ccap4l=0eeh 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 ch address 0f9h 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 cl address 0e9h 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0
rev. f - 15 february, 2001 28 t89c51rd2 figure 9. pca capture mode 6.5.2. 16-bit software timer / compare mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 10). cf cr ccon 0xd8 ch cl ccapnh ccapnl ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca counter/timer ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture
29 rev. f - 15 february, 2001 t89c51rd2 figure 10. pca compare mode and pca watchdog timer before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could happen. writing to ccapnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesnt occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. 6.5.3. high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 11). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match ccon 0xd8 pca it enable pca counter/timer reset * cidl cps1 cps0 ecf cmod 0xd9 wdte * only for module 4 reset write to ccapnl write to ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 10
rev. f - 15 february, 2001 30 t89c51rd2 figure 11. pca high speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, otherwise an unwanted match could happen. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesnt occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. 6.5.4. pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 12 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0
31 rev. f - 15 february, 2001 t89c51rd2 sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. figure 12. pca pwm mode 6.5.5. pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. figure 10 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the pca timer, 2. periodically change the pca timer value so it will never match the compare values, or 3. disable the watchdog by clearing the wdte bit before a match occurs and then re-enable it. the first two options are more reliable because the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca modules are being used. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most applications the first solution is the best option. this watchdog timer wont generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n= 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8 bit comparator cexn 0 1 3 < enable pca counter/timer over?ow
rev. f - 15 february, 2001 32 t89c51rd2 6.6. serial i/o port the serial i/o port in the t89c51rd2 is compatible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: framing error detection automatic address recognition 6.6.1. framing error detection framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). to enable the framing bit error detection feature, set smod0 bit in pcon register (see figure 13). figure 13. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register (see table 15.) bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset can clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 14. and figure 15.). figure 14. uart timings in mode 1 ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control (smod0 = 0) set fe bit if stop bit is 0 (framing error) (smod0 = 1) scon (98h) pcon (87h) data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1
33 rev. f - 15 february, 2001 t89c51rd2 figure 15. uart timings in modes 2 and 3 6.6.2. automatic address recognition the automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). 6.6.3. given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains dont-care bits (defined by zeros) to form the devices given address. the dont-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr 0101 0110b saden 1111 1100b given 0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a: saddr 1111 0001b saden 1111 1010b given 1111 0x0xb slave b: saddr 1111 0011b saden 1111 1001b given 1111 0xx1b slave c: saddr 1111 0010b saden 1111 1101b given 1111 00x1b ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
rev. f - 15 february, 2001 34 t89c51rd2 the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a dont-care bit; for slaves b and c, bit 0 is a 1. to communicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 1; for slaves b and c, bit 1 is a dont care bit. to communicate with slaves b and c, but not slave a, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). 6.6.4. broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as dont-care bits, e.g.: saddr 0101 0110b saden 1111 1100b broadcast =saddr or saden 1111 111xb the use of dont-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a: saddr 1111 0001b saden 1111 1010b broadcast 1111 1x11b, slave b: saddr 1111 0011b saden 1111 1001b broadcast 1111 1x11b, slave c: saddr= 1111 0010b saden 1111 1101b broadcast 1111 1111b for slaves a and b, bit 2 is a dont care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. 6.6.5. reset addresses on reset, the saddr and saden registers are initialized to 00h, i.e. the given and broadcast addresses are xxxx xxxxb (all dont-care bits). this ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. saden - slave address mask register (b9h) reset value = 0000 0000b not bit addressable saddr - slave address register (a9h) reset value = 0000 0000b not bit addressable table 15. scon register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
35 rev. f - 15 february, 2001 t89c51rd2 scon - serial control register (98h) reset value = 0000 0000b bit addressable 7 6 5 4 3 2 1 0 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. smod0 must be set to enable access to the fe bit sm0 serial port mode bit 0 refer to sm1 for serial port mode selection. smod0 must be cleared to enable access to the sm0 bit 6 sm1 serial port mode bit 1 sm0 sm1 mode description baud rate 0 0 0 shift register f xtal /12 (/6 in x2 mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f xtal /64 or f xtal /32 (/32 or 16 in x2 mode) 1 1 3 9-bit uart variable 5 sm2 serial port mode 2 bit / multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. this bit should be cleared in mode 0. 4 ren reception enable bit clear to disable serial reception. set to enable serial reception. 3 tb8 transmitter bit 8 / ninth bit to transmit in modes 2 and 3. clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2 rb8 receiver bit 8 / ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. in mode 1, if sm2 = 0, rb8 is the received stop bit. in mode 0 rb8 is not used. 1 ti transmit interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 ri receive interrupt ?ag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 14. and figure 15. in the other modes.
rev. f - 15 february, 2001 36 t89c51rd2 table 16. pcon register pcon - power control register (87h) reset value = 00x1 0000b not bit addressable power-off flag reset value will be 1 only after a power on (cold reset). a warm reset doesnt affect the value of this bit. 7 6 5 4 3 2 1 0 smod1 smod0 - pof gf1 gf0 pd idl bit number bit mnemonic description 7 smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6 smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to to select fe bit in scon register. 5 - reserved the value read from this bit is indeterminate. do not set this bit. 4 pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3 gf1 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2 gf0 general purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1 pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0 idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
rev. f - 15 february, 2001 37 t89c51rd2 6.7. interrupt system the t89c51rd2 has a total of 7 interrupt vectors: two external interrupts ( int0 and int1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the pca global interrupt. these interrupts are shown in figure 16. figure 16. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (see table 18.). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the interrupt priority register (see table 19.) and in the interrupt priority high register (see table 20.). shows the bit values and priority levels associated with each combination. the pca interrupt vector is located at address 0033h. all other vectors addresses are the same as standard c52 devices. ie1 0 3 high priority interrupt interrupt polling sequence, decreasing from high to low priority low priority interrupt global disable individual enable exf2 tf2 ti ri tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 0 3 pca it
38 rev. f - 15 february, 2001 t89c51rd2 table 17. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cant be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 18. ie register ie - interrupt enable register (a8h) reset value = 0000 0000b bit addressable iph.x ip.x interrupt level priority 0 0 0 (lowest) 0 1 1 1 0 2 1 1 3 (highest) 7 6 5 4 3 2 1 0 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7 ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 ec pca interrupt enable bit clear to disable . set to enable. 5 et2 timer 2 over?ow interrupt enable bit clear to disable timer 2 over?ow interrupt. set to enable timer 2 over?ow interrupt. 4 es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3 et1 timer 1 over?ow interrupt enable bit clear to disable timer 1 over?ow interrupt. set to enable timer 1 over?ow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1 et0 timer 0 over?ow interrupt enable bit clear to disable timer 0 over?ow interrupt. set to enable timer 0 over?ow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
rev. f - 15 february, 2001 39 t89c51rd2 table 19. ip register ip - interrupt priority register (b8h) reset value = x000 0000b bit addressable 7 6 5 4 3 2 1 0 - ppc pt2 ps pt1 px1 pt0 px0 bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 ppc pca interrupt priority bit refer to ppch for priority level. 5 pt2 timer 2 over?ow interrupt priority bit refer to pt2h for priority level. 4 ps serial port priority bit refer to psh for priority level. 3 pt1 timer 1 over?ow interrupt priority bit refer to pt1h for priority level. 2 px1 external interrupt 1 priority bit refer to px1h for priority level. 1 pt0 timer 0 over?ow interrupt priority bit refer to pt0h for priority level. 0 px0 external interrupt 0 priority bit refer to px0h for priority level.
40 rev. f - 15 february, 2001 t89c51rd2 table 20. iph register iph - interrupt priority high register (b7h) reset value = x000 0000b not bit addressable 7 6 5 4 3 2 1 0 - ppch pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 ppch pca interrupt priority bit high. ppch ppc priority le v el 0 0 lowest 01 10 1 1 highest 5 pt2h timer 2 over?ow interrupt priority high bit pt2h pt2 priority le v el 0 0 lowest 01 10 1 1 highest 4 psh serial port priority high bit psh ps priority le v el 0 0 lowest 01 10 1 1 highest 3 pt1h timer 1 over?ow interrupt priority high bit pt1h pt1 priority le v el 0 0 lowest 01 10 1 1 highest 2 px1h external interrupt 1 priority high bit px1h px1 priority le v el 0 0 lowest 01 10 1 1 highest 1 pt0h timer 0 over?ow interrupt priority high bit pt0h pt0 priority le v el 0 0 lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0 priority le v el 0 0 lowest 01 10 1 1 highest
rev. f - 15 february, 2001 41 t89c51rd2 6.8. idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirely : the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occured during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 6.9. power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 13, pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power-down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 17.. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put lynx/fox into power-down mode. figure 17. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase
42 rev. f - 15 february, 2001 t89c51rd2 this table shows the state of ports during idle and power-down modes. * port 0 can forc e a 0 level. a "one" will leave port floating. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data* port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port dat* port data port data port data power down external 0 0 floating port data port data port data
rev. f - 15 february, 2001 43 t89c51rd2 6.10. hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be subjected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output reset high pulse at the rst-pin. 6.10.1. using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset the device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t osc , where t osc = 1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16ms to 2s @ f osc = 12mhz. to manage this feature, refer to wdtprg register description, table 22. (sfr0a7h). table 21. wdtrst register wdtrst address (0a6h) write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 7 6 5 4 3 2 1 reset value x x x x x x x
44 rev. f - 15 february, 2001 t89c51rd2 table 22. wdtprg register wdtprg address (0a7h) reset value xxxx x000 6.10.2. wdt during power down and idle in power down mode the oscillator stops, which means the wdt also stops. while in power down mode the user does not need to service the wdt. there are 2 methods of exiting power down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power down mode. when power down is exited with hardware reset, servicing the wdt should occur as it normally should whenever the t89c51rd2 is reset. exiting power down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting the t89c51rd2 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. if the wdt is activated, the power consumption in stand-by mode will be above the specified value. 7 6 5 4 3 2 1 0 t4 t3 t2 t1 t0 s2 s1 s0 bit number bit mnemonic description 7 t4 reserved the value read from this bit is undeterminated. do not try to set this bit.. 6 t3 5 t2 4 t1 3 t0 2 s2 wdt time-out select bit 2 1 s1 wdt time-out select bit 1 0 s0 wdt time-out select bit 0 s2 s1 s0 selected t ime-out 000 (2 14 - 1) machine cycles, 16.3 ms @ 12 mhz 001 (2 15 - 1) machine cycles, 32.7 ms @ 12 mhz 010 (2 16 - 1) machine cycles, 65.5 ms @ 12 mhz 011 (2 17 - 1) machine cycles, 131 ms @ 12 mhz 100 (2 18 - 1) machine cycles, 262 ms @ 12 mhz 101 (2 19 - 1) machine cycles, 542 ms @ 12 mhz 110 (2 20 - 1) machine cycles, 1.05 s @ 12 mhz 111 (2 21 - 1) machine cycles, 2.09 s @ 12 mhz
rev. f - 15 february, 2001 45 t89c51rd2 6.11. once (tm) mode (on chip emulation) the once mode facilitates testing and debugging of systems using t89c51rd2 without removing the circuit from the board. the once mode is invoked by driving certain pins of the t89c51rd2; the following sequence must be exercised: pull ale low while the device is in reset (rst high) and psen is high. hold ale low as rst is deactivated. while the t89c51rd2 is in once mode, an emulator or test cpu can be used to drive the circuit. table 23. shows the status of the port pins during once mode. normal operation is restored when normal reset is applied. table 23. external pin status during once mode (a) "once" is a registered trademark of intel corporation. ale psen port 0 port 1 port 2 port 3 xtal1/2 weak pull-up weak pull-up float weak pull-up weak pull-up weak pull-up active
rev. f - 15 february, 2001 46 t89c51rd2 6.12. reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0. as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. table 24. auxr register auxr - auxiliary register (8eh) reset value = xx0x 1000b not bit addressable 7 6 5 4 3 2 1 0 - - m0 - xrs1 xrs0 extram ao bit number bit mnemonic description 7 - reserved the value read from this bit is indeterminate. do not set this bit. 6 - reserved the value read from this bit is indeterminate. do not set this bit. 5 m0 m0 bit: pulse length in clock period stretch movx control: the rd/ and the wr/ pulse length is increased according to the value of m0. see table 6 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 xrs1 xrs1 bit xram size: accessible size of the xram. see table 6. 2 xrs0 xrs0 bit xram size: accessible size of the xram. table 6. 1 extram extram bit see table 6. 0 ao ale output bit clear to restore ale operation during internal fetches. set to disable ale operation during internal fetches.
rev. f - 15 february, 2001 47 t89c51rd2 7. eeprom data memory 7.1. general description the eeprom memory block contains 2048 bytes and is organized in 32 pages (or rows) of 64 bytes. the necessary high programming voltage is generated on-chip using the standard vcc pin of the microcontroller. the eeprom memory block is located at the addresses 0000h to 07ffh of the xram memory space and is selected by setting control bits in the eecon register. a read in the eeprom memory is done with a movx instruction. a physical write in the eeprom memory is done in two steps : write data in the column latches and transfer of all data latches in a eeprom memory row (programming). the number of data written in the page may vary from 1 to 64 (the page size). when programming, only the data written in the column latch are programmed. this provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. 7.2. write data in the column latches data is written by byte to the column latches as if it was in an external ram memory. out of the 16 address bits of the data pointer, the 10 msb are used for page selection and 6 are used for byte selection. between two eeprom programming, all addresses in the column latches must remain in the same page, thus the 10msb must be unchanged. the following procedure is used to write in the colums latches : map the program space (set bit eee of eecon register) load dptr with the address to write load a register with the data to be written execute a movx @dptr, a if needed loop the three last instructions until the end of a 64bytes page 7.3. programming the eeprom programming consists on the following actions : write one or more bytes in a page in the column latches. normally, all bytes must belong to the same page; if this is not the case, the first page address is latched and the others are discarded. set eetim with the value corresponding to the xtal frequency. launch the programming by writing the control sequence (52h or 50h followed by a2h or a0h) to the eecon register (see table 25). eebusy flag in eecon is then set by hardware to indicate that programming is in progress and that eeprom segment is not available for read. the end of programming is signaled by a hardware clear of the eebusy flag.
48 rev. f - 15 february, 2001 t89c51rd2 example : ..... ; dptr = eeprom data pointer , a = data to write wait : mov a,eecon anl a,#01h jnz wait mov eetim,#3ch ; 12mhz*5 = 3ch mov eecon,#02h ; eee=1 eeprom mapped movx @dptr,a ; write data to eeprom mov eecon,#50h or 52h ; write sequence mov eecon,#a0h or a2h .... 7.4. read data the following procedure is used to read the data store in the eeprom memory: map the program space (set bit eee of eecon register) load dptr with the address to read execute a movx a, @dptr example : ... ; dptr = eeprom data pointer mov eecon,#02h ; eee=1 eeprom mapped movx a,@dptr ; read data from eeprom ... ; a = data 7.5. registers table 25. eecon register eecon (s: 0d2 h) eeprom control register reset value= xxxx xx00b 76543210 eepl3 eepl2 eepl1 eepl0 - - eee eebusy bit number bit mnemonic description 7-4 eepl3-0 programming launch command bits write 5xh followed by axh to eecon to launch the programming. 3 - not implemented, reserved for future use. a a. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. 2 - not implemented, reserved for future use. b b. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. 1 eee enable eeprom space bit set to map the eeprom space during movx instructions (write in the column latches) clear to map the data space during movx. 0 eebusy programming busy flag set by hardware when programming is in progress. cleared by hardware when programming is done. can not be set or cleared by software.
rev. f - 15 february, 2001 49 t89c51rd2 table 26. eetim register eetim (s: 0d3 h) eeprom timing control register reset value= 0000 0000b 76543210 eetim bit number bit mnemonic description 7-0 eetim write timer register the write timer register value is required to adapt the write time to the oscillator frequency value = 5 * fxtal (mhz) in normal mode, 10 * fxtal in x2 mode. example : fxtal = 33 mhz, eetim = 0a5h
rev. f - 15 february, 2001 50 t89c51rd2 8. flash eeprom memory 8.1. general description the flash memory increases eprom and rom functionality with in-circuit electrical erasure and programming. it contains 64k bytes of program memory organized in 512 pages of 128 bytes. this memory is both parallel and serial in-system programmable (isp). isp allows devices to alter their own program memory in the actual end product under software control. a default serial loader (bootloader) program allows isp of the flash. the programming does not require 12v external programming voltage. the necessary high programming voltage is generated on-chip using the standard v cc pins of the microcontroller. 8.2. features flash e2prom internal program memory. the last 1k bytes of the flash is used to store the low-level in-system programming routines and a default serial loader. if the application does not need to use the isp and does not expect to modify the flash content, the boot flash sector can be erased to provide access to the full 64k byte flash memory. boot vector allows user provided flash loader code to reside anywhere in the flash memory space. this configuration provides flexibility to the user. default loader in boot flash allows programming via the serial port without the need of a user provided loader. up to 64k byte external program memory if the internal program memory is disabled (ea = 0). programming and erase voltage with standard 5v or 3v v cc supply. read/programming/erase: byte-wise read (without wait state). byte or page erase and programming (10 ms). typical programming time (63k bytes) in 20 s. parallel programming with 87c51 compatible hardware interface to programmer. programmable security for the code in the flash. 100k write cycles 10 years data retention 8.3. flash programming and erasure the 64k bytes flash is programmed by bytes or by pages of 128 bytes. it is not necessary to erase a byte or a page before programming. the programming of a byte or a page includes a self erase before programming. there are three methods to program the flash memory: first, the on-chip isp bootloader may be invoked which will use low level routines to program the pages. the interface used for serial downloading of flash is the uart. second, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the boot loader. third, the flash may be programmed using the parallel method by using a conventional eprom programmer. the parallel programming method used by these devices is similar to that used by eprom 87c51 but it is not identical and the commercially available programmers need to have support for the t89c51rd2.
51 rev. f - 15 february, 2001 t89c51rd2 the bootloader and the in application programming (iap) routines are located in the last kilobyte of the flash, leaving 63k bytes available for the application with isp. 8.4. flash registers and memory map the t89c51rd2 flash memory uses several registers for his management: flash control register is used to select the flash memory spaces and launch the flash programming sequence. hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. software registers are in a special page of the flash memory which can be accessed through the api or with the parallel programming modes. this page, called "extra flash memory", is not in the internal flash program memory addressing space. 8.4.1. flash register fcon (s:d1h) flash control register reset value = xxxx 0000b figure 18. fcon register the flash programming application note and api source code are available on request. 8.4.2. hardware register the only hardware register of the t89c51rd2 is called hardware security byte (hsb). after full flash erasure, the content of this byte is ffh; each bit is active at low level. 76543210 fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy bit number bit mnemonic description 7-4 fpl3:0 programming launch command bits write 5h followed by ah to launch the programming. 3 fps flash map program space clear to map the data space during movx set to map the flash space during movx (write) or movc (read) instructions (write in the column latches) 2-1 fmod1:0 flash mode select the addressed space 00: user (0000h-ffffh) 01: xaf 10: hardware byte 11: reserved 0 fbusy flash busy set by hardware when programming is in progress. clear by hardware when programming is done. can not be cleared by software
rev. f - 15 february, 2001 52 t89c51rd2 8.4.2.1. boot loader lock bit (bllb) one bit of the hsb is used to secure by hardware the internal boot loader sector against software reprogramming. when the bllb is cleared, any attempt to write in the boot loader segment (address fc00h to ffffh) will have no effect. this protection applies for software writing only. boot loader jump bit (bljb) one bit of the hsb, the bljb bit, is used to force the boot address: when this bit is set the boot address is 0000h. when this bit is reset the boot address is fc03h. by default, this bit is cleared and the isp is enabled. 8.4.2.2. flash memory lock bits the three lock bits provide different levels of protection for the on-chip code and data, when programmed according to table 29. table 27. hardware security byte (hsb) 7 6 5 4 3 2 1 0 sb bljb bllb - - lb2 lb1 lb0 bit number bit mnemonic description 7 sb safe bit this bit must be cleared to secure the content of the hsb. only security level can be increased. 6 bljb boot loader jump bit set to force hardware boot address at 0000h. (unless previously force by hardware conditions as described in the chapter 9.6). clear to force hardware boot address at fc03h (default). 5 bllb boot loader lock bit set to allow programming and writing of the boot loader segment. clear to forbid software programming and writing of the boot loader segment (default). this protection protect only isp or iap access; protection through parallel access is done globally by the lock bits lb2-0. 4 - reserved do not clear this bit. 3 - reserved do not clear this bit. 2-0 lb2-0 user memory lock bits see table 29
53 rev. f - 15 february, 2001 t89c51rd2 table 28. program lock bits u: unprogrammed or "one" level. p: programmed or "zero" level. x:do not care warning: security level 2 and 3 should only be programmed after flash and code verification. these security bits protect the code access through the parallel programming interface. they are set by default to level 4. the code access through the isp is still possible and is controlled by the "software security bits" which are stored in the extra flash memory accessed by the isp firmware. to load a new application with the parallel programmer, a chip erase must first be done. this will set the hsb in its inactive state and will erase the flash memory, including the boot loader and the "extra flash memory" (xaf). if needed, the 1k boot loader and the xaf content must be programmed in the flash; the code is provided by atmel wireless and microcontrollers (see section 8.7. ); the part reference can always be read using flash parallel programming modes. 8.4.2.3. default values the default value of the hsb provides parts ready to be programmed with isp: sb: cleared to secure the content of the hsb. bljb: cleared to force isp operation. bllb: clear to protect the default boot loader. lb2-0: security level four to protect the code from a parallel access with maximum security. 8.4.3. software registers several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. these values are used by atmel wireless and microcontrollers isp (see section 8.7. ). these registers are in the "extra flash memory" part of the flash memory. this block is also called "xaf" or extra array flash. they are accessed in the following ways: commands issued by the parallel memory programmer. commands issued by the isp software. calls of api issued by the application software. program lock bits protection description security level lb0 lb1 lb2 1 u u u no program lock features enabled. movc instruction executed from external program memory returns non encrypted data. 2 p u u movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further parallel programming of the flash is disabled.isp and software programming with api are still allowed. 3 x p u same as 2, also verify through parallel programming interface is disabled. 4 x x p same as 3, also external execution is disabled.
rev. f - 15 february, 2001 54 t89c51rd2 they are several software registers described in table 29 table 29. default values after programming the part by isp, the bsb must be reset (00h) in order to allow the application to boot at 0000h. the content of the software security byte (ssb) is described in table 30 and table 31 to assure code protection from a parallel access, the hsb must also be at the required level. the three lock bits provide different levels of protection for the on-chip code and data, when programmed according to table 31. mnemonic default value bsb boot status byte ffh sbv software boot vector fch hsb copy of the hardware security byte 18h or 1bh ssb software security byte ffh copy of the manufacturer code 58h atmel wireless and microcontrollers copy of the device id #1: family code d7h c51 x2, electrically erasable copy of the device id #2: memories size and type fch t89c51rd2 memories size copy of the device id # 3: name and revi- sion ffh t89c51rd2 , revision 0 table 30. software security byte (ssb) 7 6 5 4 3 2 1 0 - - - lb1 - - - lb0 bit number bit mnemonic description 7 - reserved do not clear this bit. 6 - reserved do not clear this bit. 5 - reserved do not clear this bit. 4 lb1 user memory lock bit see table 31 1-3 - reserved do not clear this bit. 0 lb0 user memory lock bit see table 31
55 rev. f - 15 february, 2001 t89c51rd2 table 31. program lock bits of the ssb u: unprogrammed or "one" level. p: programmed or "zero" level. x:do not care warning: security level 2 and 3 should only be programmed after flash and code verification. 8.5. flash memory status t89c51rd2 parts are delivered in standard with the isp boot in the flash memory. after isp or parallel programming, the possible contents of the flash memory are summarized on the figure below: figure 19. flash memory possible contents 8.6. boot process boot loader flash when the user application programs its own flash memory, all of the low level details are handled by a code that is permanently contained in a 1k byte boot flash and is located in the last kilobyte of the flash memory from fc00h to ffffh (see figure 20). a user program simply calls the common entry point in the boot flash with appropriate parameters to accomplish the desired operation. boot flash operations include functions like: program lock bits protection description security level lb0 lb1 1 u u no program lock features enabled. 2 p u following commands are disabled: - program byte - program status byte and boot vector - erase status byte and boot vector 3 x p same as 2 and following commands also disabled: - read byte - read status byte and boot vector - blank check - program ssb level2 0000h boot virgin fc00h default boot boot virgin boot virgin after isp after parallel programming after parallel programming after parallel programming application application boot virgin after isp or appli or appli or appli dedicated isp dedicated isp
rev. f - 15 february, 2001 56 t89c51rd2 erase block, program byte or page, verify byte or page, program security lock bit, etc. the boot flash can be locked to prevent erasing. if erased, the boot flash can be restored by parallel programming. indeed, atmel wireless and microcontrollers provides the binary code of the default flash boot loader (see section 8.7. ). figure 20. boot loader memory map reset code execution at the falling edge of reset (unless the hardware conditions on psen, ea and ale are set as described below), the t89c51rd2 reads the bljb bit in the hsb byte. if this bit is set, it jumps to 0000h and if not, it jumps to fc03h. at this address, the boot software reads two special flash registers: the software boot vector (sbv) and the boot status byte (bsb). if the bsb is set to zero, power-up execution starts at location 0000h, which is the normal start address of the users application code. when the status byte is set to a value other than zero, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is fch, corresponding to the address fc00h for the factory default flash isp boot loader. a custom boot loader can be written with the boot vector set to the custom boot loader address. it is recommanded to set the bsb before any other iap so the device automatically resumes isp when reset. isp routines shall only clear bsb after succesfull iap completion. hardware activation of the boot loader the default boot loader can also be executed by holding psen low, ea high, and ale high (or not connected) at the falling edge of reset. this has the same effect as having a non-zero status byte anf the boot vector equal to fch. this allows an application to be built that will normally execute the end users code but can be manually forced into default isp operation. as psen has the same structure as p1-p3, the current to force psen to 0 as itl is defined in the dc parameters. if the factory default setting for the boot vector (fch) is changed, it will no longer point to the isp default flash boot loader code. it can be restored: with the default isp activated with hardware conditions on psen, ea and ale. with a customized loader (in the end user application) that provides features for erasing and reprogramming of the boot vector and bsb. through the parallel programming method. after programming the flash, the status byte should be programmed to zero in order to allow execution of the users application code beginning at address 0000h. fff0 fc00 fc03 entry point for api status byte check isp start
57 rev. f - 15 february, 2001 t89c51rd2 boot process summary the boot process is summarized on the following flowchart: figure 21. boot process flowchart custom boot loader - bsb: boot status byte - bljb: boot loader jump bit (hardware bit set to 0 by default) jump to fc00h default boot loader jump to 0000h user application jump to xx00h bljb = 1 ? software boot vector ? bsb ? hardware conditions ? yes ( psen =0, ea =1, and ale =1 or not connected) yes bsb= 0 sbv= fch sbv fch 1 xxh = no hardware software reset falling edge jump to fc03h no bsb 00 h 1
rev. f - 15 february, 2001 58 t89c51rd2 8.7. in-system programming (isp) the in-system programming (isp) is performed without removing the microcontroller from the system. the in- system programming (isp) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the t89c51rd2 through the serial port. this firmware is embedded within each t89c51rd2 device going out of factory. the atmel wireless and microcontrollers in-system programming (isp) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses four pins: txd, rxd, v ss ,v cc . only a small connector needs to be available to interface the application to an external circuit in order to use this feature. application schematic can found be in the demonstration and isp board user manual. using the in-system programming (isp) the isp feature allows a wide range of baud rates in the user application. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the t89c51rd2 to establish the baud rate. the isp firmware provides auto-echo of received characters. once baud rate initialization has been performed, the isp firmware will only accept intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: :nnaaaarrdd..ddcc in the intel hex record, the nn represents the number of data bytes in the record. the t89c51rd2 will accept up to 16 (10h) data bytes. the aaaa string represents the address of the first byte in the record. if there are zero bytes in the record, this field is often set to 0000. the rr string indicates the record type. a record type of 00 is a data record. a record type of 01 indicates the end-of-file mark. in this application, additional record types will be added to indicate either commands or data for the isp facility. the dd string represents the data bytes. the maximum number of data bytes in a record is limited to 16 (decimal). the cc string represents the checksum byte. isp commands are summarized in table 32. as a record is received by the t89c51rd2, the information in the record is stored internally and a checksum calculation is performed and compared to cc. the operation indicated by the record type is not performed until the entire record has been received. should an error occur in the checksum, the t89c51rd2 will send an x out the serial port indicating a checksum error. if the checksum calculation is found to match the checksum in the record, then the command will be executed. in most cases, successful reception of the record will be indicated by transmitting a . character out the serial port (displaying the contents of the internal program memory is an exception). in the case of a data record (record type 00), an additional check is made. a . character will not be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. for a data record, an x indicates that the checksum failed to match, and an r character indicates that one of the bytes did not properly program. atmel wireless and microcontrollers_isp, a software utility to implement isp programming with a pc, is available from atmel wireless and microcontrollers. please visit our web site http://www.atmel-wm.com.
59 rev. f - 15 february, 2001 t89c51rd2 table 32. intel-hex records used by in-system programming record type command/data function 00 data record :nnaaaa00dd....ddcc where: nn = number of bytes (hex) in record aaaa = memory address of first byte in record dd....dd = data bytes cc = checksum example: :05008000af5f67f060b6 (program address 80h to 85h with data af ... 60) 01 end of file (eof), no operation :xxxxxx01cc where: xxxxxx = required field, but value is a dont care cc = checksum example: :00000001ff 02 specify oscillator frequency (not required, left for philips compatibility) :01xxxx02ddcc where: xxxx = required field, but value is a dont care dd = required field, but value is a dont care cc = checksum example: :0100000210ed
rev. f - 15 february, 2001 60 t89c51rd2 03 miscellaneous write functions :nnxxxx03ffssddcc where: nn = number of bytes (hex) in record xxxx = required field, but value is a dont care 03 = write function ff = subfunction code ss = selection code dd = data input (as needed) cc = checksum subfunction code = 04 (reset boot vector and status byte) ff = 04 ss = dont care dd = dont care example: :020000030400f8 reset boot vector (fch) and status byte (ffh) subfunction code = 05 (program software security bits) ff = 05 ss = 00 program software security bit 1 (level 2 inhibit writing to flash) ss = 01 program software security bit 2 (level 3 inhibit flash verify) ss = 02 program security bit 3 (no effect, left for philips compatibity; disable external memory is already set in the default hardware security byte) example: :020000030501f6 program security bit 2 subfunction code = 06 (program status byte or boot vector) ff = 06 ss = 00 program bsb ss = 01 program boot vector example: :03000003060100f5 program boot vector with 00 subfunction code = 07 (full chip erase) ff = 07 example: :0100000307f5 full chip erase (include boot vector / status byte and software security bit erase) 04 display device data or blank check record type 04 causes the contents of the entire flash array to be sent out the serial port in a formatted display. this display consists of an address and the contents of 16 bytes starting with that address. no display of the device contents will occur if security bit 2 has been programmed. the dumping of the device data to the serial port is terminated by the reception of any character. general format of function 04 :05xxxx04sssseeeeffcc where: 05 = number of bytes (hex) in record xxxx = required field, but value is a dont care 04 = display device data or blank check function code ssss = starting address eeee = ending address ff = subfunction 00 = display data 01 = blank check cc = checksum example: :0500000440004fff0069 (display 4000C4fff) table 32. intel-hex records used by in-system programming
61 rev. f - 15 february, 2001 t89c51rd2 8.8. in-application programming method several application program interface (api) calls are available for use by an application program to permit selective erasing and programming of flash pages. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontrollers registers before making a call to pgm_mtp at fff0h. results are returned in the registers. the api calls are shown in table 33. a set of philips compatible api calls is provided. when several bytes have to be programmed, it is highly recommanded to use the atmel wireless and microcontrollers api program data page call. indeed, this api call writes up to 128 bytes in a single command. 05 miscellaneous read functions general format of function 05 :02xxxx05ffsscc where: 02 = number of bytes (hex) in record xxxx = required field, but value is a dont care 05= miscellaneous read function code ffss = subfunction and selection code 0000 = read copy of the signature byte C manufacturer id (58h) 0001 = read copy of the signature byte C device id# 1 (family code) 0002 = read copy of the signature byte C device i d # 2 (memories size and type) 0003 = read copy of the signature byte C device i d # 3 (product name and revision) 0700 = read the software security bits 0701 = read status byte (bsb) 0702 = read boot vector (sbv) 0703 = read copy of the hsb 0800 = read bootloader version cc = checksum example: :020000050001f0 read copy of the signature byte C device id # 1 table 33. api calls api call parameter program data byte input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 02h dptr = address of byte to program acc = byte to program return parameter acc = 00 if pass, !00 if fail table 32. intel-hex records used by in-system programming
rev. f - 15 february, 2001 62 t89c51rd2 program data page input parameters: r0 = osc freq (integer not required) r1 = 09h dptr0 = address of the first byte to program in the flash memory dptr1 = address in xram of the first data to program (second data pointer) acc = number of bytes to program return parameter acc = 00 if pass, !00 if fail remark: number of bytes to program is limited such as the flash write remains in a single 128bytes page. hence, when acc is 128, valid values of dpl are 00h, or, 80h. erase boot vector status byte input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 04h dph = 00h dpl = dont care return parameter none program software security bit input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 05h dph = 00h dpl = 00h C security bi t # 1 (inhibit writing to flash) 01h C security bi t # 2 (inhibit flash verify) 10h - allows isp writing to flash* 11h - allows isp flash verify* return parameter none program boot status byte input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 06h dph = 00h dpl = 00h C program status byte acc = status byte return parameter acc = status byte program boot vector input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 06h dph = 00h dpl = 01h C program boot vector acc = boot vector return parameter acc = boot vector read device data input parameters: r1 = 03h dptr = address of byte to read return parameter acc = value of byte read read copy of the manufacturer id input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 00h dph = 00h dpl = 00h (manufacturer id) return parameter acc = value of byte read table 33. api calls
63 rev. f - 15 february, 2001 t89c51rd2 api call parameter read copy of the device id#1 input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 00h dph = 00h dpl = 01h (device id # 1) return parameter acc = value of byte read read copy of the device id#2 input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 00h dph = 00h dpl = 02h (device id # 2) return parameter acc = value of byte read read copy of the device id#3 input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 00h dph = 00h dpl = 03h (device id # 2) return parameter acc = value of byte read read software security bits input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 07h dph = 00h dpl = 00h (software security bits) return parameter acc = value of byte read read copy of the hardware security bits input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 07h dph = 00h dpl = 03h (hardtware security bits) return parameter acc = value of byte read read boot vector input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 07h dph = 00h dpl = 02h (boot vector) return parameter acc = value of byte read read bootloader version input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 08h return parameter acc = value of byte read read boot status byte input parameters: r0 = osc freq (integer not required, left for philips compatibility) r1 = 07h dph = 00h dpl = 01h (status byte) return parameter acc = value of byte read table 33. api calls
rev. f - 15 february, 2001 64 t89c51rd2 note: these functions can only be called by users code. the standard boot loader cannot decrease the security level. 8.9. flash parallel programming 8.9.1. signature bytes four hardware read only registers have to be accessed with parallel static test modes (mode tms) in order to control the flash parallel programmimg: manufacturer code device id # 1: family code device id # 2: memories size and type device id # 3: name and revision as these registers can only be accessed by hardware, they must be read by the parallel programmers and then copied in the xaf in order to make their values accessible by software (isp or api). 8.9.2. set-up modes in order to program and verify the flash or to read the signature bytes, the t89c51rd2 is placed in specific set-up modes (see figure 22). control and program signals must be held at the levels indicated in table 37. and table 38.(please notice that each mode is defined over the two tables
65 rev. f - 15 february, 2001 t89c51rd2 mode name mode rst psen ale __ |_| ea p2.6 p2.7 p3.6 p3.7 p0[7..0] pelck program or erase lock. disable the erasure or programming access 10 __ |_| 1 1 0 1 0 xx peulck program or erase unlock. enable the erasure or programming access 1 0 note3 1 1 0 1 0 55-aa pgmc write code data (byte) or write page always precedeed by pgml 10 __ |_| internally timed 10111 xx pgml memory page load (up to 128 bytes) 1 0 note2 1 0 1 0 1 din pgmv read code data (byte) 1 0 1 1 0 __ |_| 1 1 dout vsb read security byte (=hsb) 1 0 1 1 0 __ |_| 0 1 dout pgms write security byte (note 4) (security byte = hsb) 1 0 10ms 1 1 1 0 0 din cerr chip erase user + xaf 1 0 10ms 1 1 0 0 0 xx pgxc write byte or page in extra memory (xaf) always precedeed by pgxl 10 __ |_| internally timed 11101 xx pgxl memory page load xaf (up to 128 bytes) 1 0 note2 1 1 1 0 1 din tms read signature bytes 30h (manufacturer code) 31h (device id #1) 60h (device id #2) 61h (device id #3) 10 1 10 __ |_| 0 0 dout = 58h d7h fch ffh rxaf read extra memory (xaf) 10 1 10 __ |_| 0 0 dout
rev. f - 15 february, 2001 66 t89c51rd2 note 1: p3.2 is pulled low during programming to indicate rdy/busy. (p3. 2 = 1 ready; p3. 2 = 0 busy). note 2: in page load mode the current byte is loaded on ale rising edge. note 3: after a power up all external test mode to program or to erase the flash are locked to avoid any untimely programming or erasure. after each programming or erasure test mode, its advised to lock this feature (test mode pelck). to validate the test mode mode peulck the following sequence has to be applied: test mode peulck with ale = 1. pulse on ale (min width=25clk) with p0=55 (p0 latched on ale rising edge) pulse on ale (min width=25clk) with p0=aa (p0 latched on ale rising edge) note 4: the highest security bit (bit 7) is used to secure the 7 lowest bit erasure. the only way to erase this bit is to erase the whole flash memory. procedure to program security bits (after array programming): - program bit7 to 0, program all other bits ( 1 = erased, 0 = programmed). - test mode pgms (din = hsb). procedure to erase security byte: - test mode cerr: erase all array included hsb. - program hardware security byte to ff: test mode pgms (din = ff). 8.9.3. definition of terms address lines: p1.0-p1.7, p2.0-p2.5, p3.4-p3.5, respectively for a0-a15. data lines: p0.0-p0.7 for d0-d7 control signals: rst, psen, p2.6, p2.7, p3.2, p3.3, p3.6, p3.7. program signals: ale/ prog, ea mode name mode p1[7..0] p2[5..0] p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 pelck program or erase lock. disable the erasure or programming access xx xx xx x 1xx peulck program or erase unlock. enable the erasure or programming access xx xx xx x 0xx pgmc write code data (byte) or write page always precedeed by pgml a7-a0 a13-a8 1 x note1 0 a14 a15 pgml memory page load (up to 128 bytes) a7-a0 a13-a8 1 x x 0 a14 a15 pgmv read code data (byte) a7-a0 a13-a8 1 x x 1 a14 a15 vsb read security byte (=hsb) xx xx 1 x x 1 x x pgms write lock byte (note 4) (security byte = hsb) xx xx 1 x note1 0 x x cerr chip erase user + xaf xx xx 1 x x 0 x x pgxc write byte or page extra memory (xaf) always precedeed by pgxl a7-a0 (0-7f) xx 1 x note1 0 x x pgxl memory page load xaf (up to 128 bytes) a7-a0 (0-7f) xx 1x x 1xx tms read signature bytes 30h (manufacturer code) 31h (device id #1) 60h (device id #2) 61h (device id #3) 30h 31h 60h 61h x xx x 1xx rxaf read extra memory (xaf) addr (0-7f) 00 1x x 0xx
67 rev. f - 15 february, 2001 t89c51rd2 figure 22. set-up modes configuration 8.9.4. programming algorithm to program the t89c51rd2 the following sequence must be exercised: check the signature bytes check the hsb (vsb mode) if the security bits are activated, the following commands must be done before programming: unlock test modes (peulck mode, pulse 55h and aah) chip erase (cerr mode) write ffh in the hsb (pgms mode) write the signature bytes content in the xaf as the boot loader and the xaf content is lost after a "chip erase", it must be reprogrammed if needed. disable programming access (pelck mode) to write a page in the flash memory, execute the following steps: step 0: enable programming access (peulck mode) step 1: activate the combination of control signals (pgml mode) step 2: input the valid address on the address lines (high order bits of the address must be stable during the complete ale low time) step 3: activate the combination of control signals (pgml mode) step 4: input the appropriate data on the data lines. step 5: pulse ale/ prog once. repeat step 2 through 5 changing the address and data for end of a 128 bytes page step 6: enable programming access (peulck mode) step 7: activate the combination of control signals (pgmc mode) +5v v cc p0.0-p0.7 p1.0-p1.7 p2.0-p2.5 vss gnd d0-d7 a0-a7 a8-a13 rst ea ale/ pr og psen p2.6 p2.7 p3.3 p3.7 p3.6 xtal1 4 to 6 mhz control signals* program signals* p3.4 a14 p3.5 a15
rev. f - 15 february, 2001 68 t89c51rd2 step 8: input the valid address on the address lines. step 9: pulse ale/ prog once until p3.2 is high or the specified write time is reached. repeat step 0 through 9 changing the address and data until the entire array or until the end of the object file is reached (see figure 23.) step 10: disable programming access (pelck mode) 8.9.5. verify algorithm verify must be done after each byte or block of bytes is programmed. in either case, a complete verify of the programmed array will ensure reliable programming of the t89c51rd2. p 2.7 is used to enable data output. to verify the t89c51rd2 code the following sequence must be exercised: step 1:activate the combination of program and control signals (pgmv) step 2: input the valid address on the address lines. step 3: read data on the data lines. repeat step 2 through 3 changing the address for the entire array verification (see figure 23.). figure 23. programming and verification signals waveform 8.9.6. extra memory mapping the memory mapping the t89c51rd2 software registers in the extra flash memory is described in the table below. table 34. extra row memory mapping (xaf) address default content copy of device id #3 0061h ffh control signals data in ale/ pr og a0-a15 programming cycle d0-d7 ea data out read/verify cycle 5v 0v p2.7 48 clk (load latch ) or 10 ms (write)
69 rev. f - 15 february, 2001 t89c51rd2 all other addresses are reserved copy of device id #2 0060h fch copy of device id #1 0031h d7h copy of manufacturer code: atmel 0030h 58h boot reference 0006h software security byte (level 1 by default) 0005h ffh copy of hsb (level 4 by default and bljb =0) 0004h 18h or 1bh software boot vector 0001h fch boot status byte 0000h ffh table 34. extra row memory mapping (xaf)
rev. f - 15 february, 2001 70 t89c51rd2 9. electrical characteristics 9.1. absolute maximum ratings (1) ambiant temperature under bias: c = commercial 0 cto70 c i = industrial -40 cto85 c storage temperature -65 c to +150 c voltage on v cc v ss -0.5 v to +6.5v voltage on any pin v ss -0.5vtov cc +0.5 v power dissipation 1 w (2) notes 1. s tresses at or above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is speci?cation is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package.
71 rev. f - 15 february, 2001 t89c51rd2 9.2. dc parameters for standard voltage (1) t a =0 cto+70 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. t a = -40 cto+85 c; v ss =0v;v cc =5v 10%;f=0to40 mhz. table 35. dc parameters in standard voltage (1) symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 and 5 (6) 0.3 0.45 1.0 v v v i ol = 100 m a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v i ol = 200 m a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) v oh output high voltage, ports 1, 2, 3, 4 and 5 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 m a i oh = -30 m a i oh = -60 m a v cc = 5 v 10% v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -200 m a i oh = -3.2 ma i oh = -7.0 ma v cc = 5 v 10% r rst rst pulldown resistor 50 90 200 k w i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 and 5 -650 m a vin = 2.0 v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 120 150 m a v cc = 3 v to 5.5 v (3) i ccop power supply current onnormal mode 0.7 freq (mhz) + 3 ma ma v cc = 5.5 v (1) i ccidle power supply current on idle mode 0.4 freq (mhz) + 2 ma ma v cc = 5.5 v (2)
rev. f - 15 february, 2001 72 t89c51rd2 9.3. dc parameters for standard voltage (2) t a =0 cto+70 c; v ss =0v;v cc =3vto5.5v;f=0to33 mhz. t a = -40 cto+85 c; v ss =0v;v cc =3vto5.5v;f=0to33 mhz. table 36. dc parameters for standard voltage (2) symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 and 5 (6) 0.45 v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.45 v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3, 4 and 5 0.9 v cc v i oh = -10 m a v oh1 output high voltage, port 0, ale, psen 0.9 v cc v i oh = -40 m a i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 and 5 -650 m a vin = 2.0 v r rst rst pulldown resistor 50 90 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 120 150 m a v cc = 3 v to 5.5 v (3) i ccop power supply current on normal mode 0.7 freq (mhz) + 3 ma ma v cc = 5.5 v (1) i ccidle power supply current on idle mode 0.5 freq (mhz) + 2 ma ma v cc = 5.5 v (2)
73 rev. f - 15 february, 2001 t89c51rd2 9.4. dc parameters for low voltage t a =0 cto+70 c; v ss =0v;v cc =2.7vto3.6v;f=0to25 mhz. t a = -40 cto+85 c; v ss =0v;v cc =2.7vto3.6v;f=0to25 mhz. table 37. dc parameters for low voltage notes 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 27.), v il = v ss + 0.5 v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used (see figure 24.). 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch ,t chcl = 5 ns, v il =v ss + 0.5 v, v ih =v cc - 0.5 v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 25.). 3. power down i cc is measured with all output pins disconnected; ea=v ss ,port0=v cc ; xtal2 nc.; rst = v ss (see figure 26.). in addition, the wdt must be inactive and the pof ?ag must be set. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature.. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3, 4 and 5 (6) 0.45 v i ol = 0.8 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.45 v i ol = 1.6 ma (4) v oh output high voltage, ports 1, 2, 3, 4 and 5 0.9 v cc v i oh = -10 m a v oh1 output high voltage, port 0, ale, psen 0.9 v cc v i oh = -40 m a i il logical 0 input current ports 1, 2, 3, 4 and 5 -50 m a vin = 0.45 v i li input leakage current 10 m a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3, 4 and 5 -650 m a vin = 2.0 v r rst rst pulldown resistor 50 90 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power down current 1 50 m a v cc = 2.7 v to 3.6 v (3) i ccop power supply current on normal mode 0.6 freq (mhz) + 3 ma ma v cc = 3.6 v (1) i ccidle power supply current on idle mode 0.3 freq (mhz) + 2 ma ma v cc = 3.6 v (2)
rev. f - 15 february, 2001 74 t89c51rd2 figure 24. i cc test condition, active mode figure 25. i cc test condition, idle mode figure 26. i cc test condition, power-down mode ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected.
75 rev. f - 15 february, 2001 t89c51rd2 figure 27. clock signal waveform for i cc tests in active and idle modes 9.5. ac parameters 9.5.1. explanation of the ac symbols each timing symbol has 5 characters. the first character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example:t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a =0to+70 c; v ss =0v;v cc =5v 10%; m range. t a = -40 cto+85 c; v ss =0v; v cc =5v 10%; m range. t a =0to+70 c; v ss =0v;2.7v rev. f - 15 february, 2001 76 t89c51rd2 9.5.2. external program memory characteristics table 38. symbol description symbol parameter t oscillator clock period t lhll ale pulse width t avll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction floatafter psen t aviv address to valid instruction in t plaz psen low to address float table 39. ac parameters for a fix clock symbol -m -l units min max min max t 25 25 ns t lhll 40 40 ns t avll 10 10 ns t llax 10 10 ns t lliv 70 70 ns t llpl 15 15 ns t plph 55 55 ns t pliv 35 35 ns t pxix 0 0 ns t pxiz 18 18 ns t aviv 85 85 ns t plaz 10 10 ns
77 rev. f - 15 february, 2001 t89c51rd2 9.5.3. external program memory read cycle table 40. ac parameters for a variable clock symbol type standard clock x2 clock x parameter for -m range x parameter for -l range units t lhll min 2 t - x t - x 10 10 ns t avll min t - x 0.5 t - x 15 15 ns t llax min t - x 0.5 t - x 15 15 ns t lliv max 4 t - x 2 t - x 30 30 ns t llpl min t - x 0.5 t - x 10 10 ns t plph min 3 t - x 1.5 t - x 20 20 ns t pliv max 3 t - x 1.5 t - x 40 40 ns t pxix min x x 0 0 ns t pxiz max t - x 0.5 t - x 7 7 ns t aviv max 5 t - x 2.5 t - x 40 40 ns t plaz max x x 10 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t aviv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
rev. f - 15 february, 2001 78 t89c51rd2 9.5.4. external data memory characteristics table 41. symbol description symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t av dv address to valid data in t llwl ale to wr or rd t avwl address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high
79 rev. f - 15 february, 2001 t89c51rd2 table 42. ac parameters for a fix clock symbol -m -l units min max min max t rlrh 130 130 ns t wlwh 130 130 ns t rldv 100 100 ns t rhdx 0 0 ns t rhdz 30 30 ns t lldv 160 160 ns t av dv 165 165 ns t llwl 50 100 50 100 ns t avwl 75 75 ns t qvwx 10 10 ns t qvwh 160 160 ns t whqx 15 15 ns t rlaz 0 0 ns t whlh 10 40 10 40 ns
rev. f - 15 february, 2001 80 t89c51rd2 9.5.5. external data memory write cycle table 43. ac parameters for a variable clock symbol type standard clock x2 clock x parameter for -m range x parameter for -l range units t rlrh min 6 t - x 3 t - x 20 20 ns t wlwh min 6 t - x 3 t - x 20 20 ns t rldv max 5 t - x 2.5 t - x 25 25 ns t rhdx min x x 0 0 ns t rhdz max 2 t - x t - x 20 20 ns t lldv max 8 t - x 4t -x 40 40 ns t av dv max 9 t - x 4.5 t - x 60 60 ns t llwl min 3 t - x 1.5 t - x 25 25 ns t llwl max 3 t + x 1.5 t + x 25 25 ns t avwl min 4 t - x 2 t - x 25 25 ns t qvwx min t - x 0.5 t - x 15 15 ns t qvwh min 7 t - x 3.5 t - x 15 15 ns t whqx min t - x 0.5 t - x 10 10 ns t rlaz max x x 0 0 ns t whlh min t - x 0.5 t - x 15 15 ns t whlh max t + x 0.5 t + x 15 15 ns t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh
81 rev. f - 15 february, 2001 t89c51rd2 9.5.6. external data memory read cycle 9.5.7. serial port timing - shift register mode table 44. symbol description symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid table 45. ac parameters for a fix clock symbol -m -l units min max min max t xlxl 300 300 ns t qvhx 200 200 ns t xhqx 30 30 ns t xhdx 0 0 ns t xhdv 117 117 ns ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t av dv
rev. f - 15 february, 2001 82 t89c51rd2 9.5.8. shift register timing waveforms table 46. ac parameters for a variable clock symbol type standard clock x2 clock x parameter for -m range x parameter for -l range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 50 ns t xhqx min 2 t - x t - x 20 20 ns t xhdx min x x 0 0 ns t xhdv max 10 t - x 5 t- x 133 133 ns valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid
83 rev. f - 15 february, 2001 t89c51rd2 9.5.9. flash eeprom programming and verification characteristics t a =21 cto27 c; v ss = 0v; v cc =5v 10%. 9.5.10. flash eeprom programming and verification waveforms table 47. flash programming parameters symbol parameter min max units 1/t clcl oscillator frquency 4 6 mhz t ehaz control to address ?oat 48 t clcl t av g l address setup to pr og low 48 t clcl t ghax adress hold after pr og 48 t clcl t dvgl data setup to pr og low 48 t clcl t ghdx data hold after pr og 48 t clcl t glgh pr og width for pgmc and pgxc* 10 20 ms t glgh pr og width for pgml 48 t clcl t avqv address to valid data 48 t clcl t elqv enable low to data valid 48 t clcl t ehqz data float after enable 0 48 t clcl t ehaz ale/prog t av g l t dvgl p0 p1.0-p1.7 p2.0-p2.4 p3.4-p3.5 control signals (enable) address data in t ghax t ghdx t glgh address data out t avqv t elqv t ehqz programming verification
rev. f - 15 february, 2001 84 t89c51rd2 9.5.11. external clock drive characteristics (xtal1) table 48. ac parameters 9.5.12. external clock drive waveforms 9.5.13. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic 1 and 0.45v for a logic 0. timing measurement are made at v ih min for a logic 1 and v il max for a logic 0. 9.5.14. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 3 20ma. symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 % v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5 v 0.45 v float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v
85 rev. f - 15 february, 2001 t89c51rd2 9.5.15. clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions extern al pr ogram memor y fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr por t opera tion mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial por t shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
rev. f - 15 february, 2001 86 t89c51rd2 10. ordering information packages: 3c: pdil40 sl: plcc44 rl: vqfp44 (1.4mm) sm: plcc68 rd: vqfp64, square- package (1.4mm) dd: dice in ship tray t -m: vcc: 4.5 to 5.5v 40mhz, x1 mode 20mhz, x2 mode vcc: 3 to 5.5v 33 mhz, x1 mode 16 mhz, x2 mode -l : vcc: 2.7 to 3.6 v 25 mhz, x1 mode 12 mhz, x2 mode s temperature range c: commercial 0 to 70 o c i: industrial -40 to 85 o c -3c conditioning s: stick t: tray r: tape & reel u: stick + dry pack v: tray + dry pack f: tape & reel + dry pack b: blue tape w: wafer m 89c51rd2 c 89c51rd2 (64k flash)

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